Subtrack

Instruction Set Architecture

Learn x86, ARM, and RISC-V at the spec level. Understand instruction encoding, calling conventions, and architectural trade-offs between CISC and RISC designs.

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~360 Minutes 8 Challenges

instruction set architecture tutorial

About this subtrack

Instruction Set work compares encodings and conventions and even sketches a small disassembler. Primary keyword: "ISA tutorial for systems programmers."

Instruction Set Architecture

About this subtrack

Tasks (8)

Understand x86-64 System V ABI Calling Conventions at CPU Level

Write Same Program in x86-64, ARM64, and RISC-V; Compare

Understand Instruction Encoding: Manually Encode 3 x86 Instructions

Write Mini Disassembler: Decode Byte Stream Back to Mnemonics

Understand CISC vs RISC Trade-offs with Benchmarks

Study RISC-V: Implement Simple RISC-V Emulator for RV32I

Understand Privileged Instructions: What Makes an Instruction 'Supervisor Only'

Explore Thumb-2 (16-bit ARM): When and Why It's Used in Embedded