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Master the fundamental concepts of instruction set architecture through this focused micro-challenge.
You have read the whole brief, and the concepts above stay free on every task. Writing and running the code needs a plan.
Three hints are available for this task, revealed one at a time inside the code workspace so you can struggle productively before seeing them.
Every task includes starter code, theory, and hidden tests so you can implement and verify locally in the browser.
How it worksPrivileged instructions touch CPU state ordinary programs must not control: page tables, interrupt masks, model-specific registers, and I/O ports. Attempting them in user mode traps to the kernel.
Examples across architectures:
WRMSR, LGDT, IN/OUT (when IOPL blocks)MSR to system registers, WFICSRRW, SFENCE.VMA, MRETcLoading…
Without privilege levels, any process could remap memory, disable interrupts, or hijack devices. Operating systems rely on ring transitions (syscall, interrupt) to enter supervisor mode safely.
For this exercise, you will classify a list of mnemonics as user-safe or supervisor-only and explain what each privileged op controls. This task asks you to connect ISA privilege bits to the protection model your OS track will build on top of.
Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.
For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.
Simulate the CPU's privilege check and the system-call path. A user program runs in ring 3 (CPL = 3). Every instruction that could let it take over the machine is supervisor-only: disabling interrupts, loading page tables, touching I/O ports or model-specific registers. The CPU refuses such an instruction with a #GP fault, and the kernel turns that into a signal. The only legal way into ring 0 is syscall. The kernel services the request and returns with sysret.
| Class | Instructions |
|---|---|
| privileged (CPL 0 only) | cli, sti, hlt, lgdt, lidt, ltr, invlpg, rdmsr, wrmsr, in, out, and any mov with a control register (cr0 cr2 cr3 cr4) as an operand |
| user-safe | mov REG, imm, add REG, imm, nop, rdtsc, syscall |
Registers rax, rdi, rsi, rdx start at 0. Operands of privileged instructions are irrelevant. Anything else is an unknown instruction.
#GP. The kernel sends SIGSEGV; the program has installed a handler that skips the instruction, so execution continues.rdtsc → rax = the number of instructions executed before this one (a deterministic timestamp counter).syscall → switch to ring 0, dispatch on rax, then sysret back to ring 3 with the result in rax:
1 write: output the byte rdi (an ASCII code); result 139 getpid: result 424260 exit: status rdi; the program ends in the kernel (no sysret)ENOSYS)Lines are numbered from 1 (blank lines are skipped and not numbered). Print only these events:
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The instruction is echoed normalised to mnemonic op1, op2. For rdtsc, an instruction that faulted counts as executed; an unknown one does not. Then:
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Each syscall is 2 transitions (in and out), except exit, which is 1.
Input:
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Output:
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required_cpl(instruction) as one classification function, and check CPL > required before executing anything.Hidden tests cover every privileged mnemonic class (including in/out, wrmsr and reading cr0), rdtsc being allowed, getpid, an unknown system call, an unknown instruction, and a program that ends without exit.