Understand CISC vs RISC Trade-offs with Benchmarks

Topic Overview

Complexity vs Regularity

CISC ISAs (x86) pack rich operations into variable-length encodings to save memory on 1980s machines with tiny RAM. RISC ISAs (ARM, RISC-V, MIPS) favor fixed-width instructions, many registers, and load/store simplicity so decode hardware stays fast and power low.

• CISC (x86): variable instruction size, rich addressing modes, high code density
• RISC (ARM/RISC-V): fixed 32-bit encodings, many GPRs, load/store discipline
• Memory operands: x86 ALU ops may touch RAM; RISC requires explicit loads and stores

Benchmark Reality

Code density favors CISC: the same C function may compile smaller on x86. Clock-for-clock on modern out-of-order cores, RISC designs win on power and decode regularity, not raw instruction count.

For this exercise, you will compile identical loops for two targets and compare static instruction counts and dynamic retired instructions (perf stat). This task asks you to ground ISA debates in measured data instead of 1990s textbook slogans.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.

Your Task

Modern x86 cores don't execute CISC instructions directly. The decoder first cracks each one into simple RISC-like micro-operations. Write that cracker for a small x86 subset. Translate each CISC instruction into load/store-architecture operations, then compare the two programs by instruction count, code size and memory traffic. The comparison shows the CISC/RISC trade-off: x86 is denser, the RISC version has more but simpler instructions, and the memory traffic is identical.

Translation table

R, R1, R2 are register names (any identifier). M is a memory operand [reg], [reg+N] or [reg-N], written in RISC form as N(reg) (0(reg) when there's no offset). imm is a decimal integer. OP is add or sub. tmp is a scratch register.

Every RISC operation is 4 bytes. ld and sd are memory accesses. A CISC instruction makes the same accesses: one per ld/sd in its translation.

Input / Output

One CISC instruction per line (lower case, operands separated by , and optional spaces). For each line:

cCopy
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CISC-TEXT is the instruction normalised to mnemonic op1, op2. A line matching no row prints CISC-TEXT -> unsupported and is excluded from the totals. Then:

cCopy
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Example

Input:

cCopy
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Output:

cCopy
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Requirements

1. Classify each operand as register, immediate or memory first; pick the table row from the (mnemonic, operand kinds) pattern.
2. Convert [reg±N] to N(reg) in one helper.

Hidden tests cover register-to-register and immediate forms, sub with an immediate, a store, inc/dec on memory, negative offsets, and unsupported forms such as memory-to-memory mov.