Study RISC-V: Implement Simple RISC-V Emulator for RV32I

Topic Overview

RV32I Base Integer ISA

RISC-V defines a modular open ISA. RV32I provides 32 registers (x0 hardwired zero), load/store, branches, and immediate arithmetic. Emulator structure mirrors your toy CPU: fetch, decode, execute.

cCopy
Loading…

Instruction Formats

• R-type: register-register ALU ops
• I-type: immediates, loads, JALR
• S/B/U/J: stores, branches, upper immediates, jumps

For example, ADDI x5, x0, 10 places decimal 10 into x5 using opcode 0x13.

For this exercise, you will implement decode and execute for a subset of RV32I and run small binaries linked for qemu-riscv32 or flat hex images. This task asks you to see how a clean encoding map simplifies decoder tables compared to x86.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.

Your Task

Write an emulator for a subset of RV32I, the RISC-V base integer ISA. It reads raw 32-bit machine-code words and decodes each one's fields: opcode, registers, funct3/funct7 and the scrambled immediates. It executes each instruction and prints a disassembled trace with the effect of every step.

Machine

• 32 registers x0: x31, 32-bit signed, all 0. x0 always reads 0, and writes to it are discarded.
• Code is the input words at addresses 0, 4, 8, …. Data memory is a separate 4 KiB (addresses 0x000: 0xfff), zero-filled, little-endian.
• Execution stops at ecall (0x00000073), an illegal instruction, a memory fault, a pc outside the program, or after 1000 instructions.

Instructions

Anything else is illegal. A lw/sw address that isn't a multiple of 4 or goes past 0xffc is a memory fault.

Output

One line per instruction: PPPP: DISASSEMBLY -> EFFECT (PPPP = 4 hex digits).

A write to x0 prints x0 unchanged. Values are signed decimal. Special endings: PPPP: ecall -> exit, PPPP: illegal instruction 0xHHHHHHHH, PPPP: lw x6, 2(x9) -> memory fault at 0x0017, pc 0xPPPP out of program, step limit reached. Finally:

cCopy
Loading…

N counts completed instructions, including ecall, but not an illegal or faulting one.

Example

Input:

cCopy
Loading…

Output:

cCopy
Loading…

Requirements

1. Extract the fields once per instruction, with one helper per immediate format (I, S, B, J) that sign-extends correctly.
2. Enforce x0 = 0 in the write-back step, not in each instruction.

Hidden tests cover jal/jalr calls and returns, lui, shifts, slt/blt, a write to x0, xori/ori/andi with negative immediates, an illegal instruction and a misaligned load.