Write Same Program in x86-64, ARM64, and RISC-V; Compare

Topic Overview

Same Algorithm, Three ISAs

Writing one function in x86-64, ARM64, and RISC-V assembly exposes how ISA design shapes code size, register pressure, and encoding complexity.

asmCopy
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Encoding and Philosophy

• x86-64 (CISC): variable-length instructions (1 to 15 bytes), rich addressing modes, decades of backward compatibility
• ARM64 (RISC): fixed 32-bit encodings, 31 GPRs, load/store architecture, tuned for power efficiency
• RISC-V (RISC): fixed 32-bit base instructions, open royalty-free spec, minimalist opcode space

For example, adding two integers might take three instructions on x86 (move, add, return) but two on ARM and RISC-V because arguments already sit in w0/a0 and w1/a1.

For this exercise, you will implement add_numbers stubs for each architecture and compare instruction counts and byte sizes. This task asks you to connect encoding differences to Apple's Arm transition and LLVM's separate backend code generators.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.

Your Task

Write a tiny code generator with three back ends. It compiles one small integer function to x86-64, ARM64 and RISC-V (RV64IM), then compares instruction counts and code size. You'll see the CISC/RISC split directly. x86 has two-operand instructions and variable-length encodings, so short immediates save bytes. ARM64 and RISC-V have three-operand instructions and every instruction is 4 bytes.

Input

One function per line:

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Up to 4 int parameters. Operands are parameter names or decimal constants 0..2047. OP is +, - or *. The expression is evaluated strictly left to right (no precedence), just like an accumulator: a + b * c means (a + b) * c.

Code generation

Parameters arrive in edi, esi, edx, ecx (x86-64), w0–w3 (ARM64) and a0–a3 (RISC-V); the result is returned in eax / w0 / a0. Every function ends with ret.

x86-64 accumulates in eax:

ARM64 / RISC-V (4 bytes each). Operation i computes DST = SRC1 op OPERAND. SRC1 is the first operand for the first operation and the previous DST after that. DST is the return register for the last operation and the temporary (w8 / t0) before it.

With no operator, the body is only the move into the return register: mov w0, wN, mov w0, #K, mv a0, aN, li a0, K. It is omitted when the operand is already the first parameter.

Output

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Print a blank line between functions. On an unknown operand, print only NAME: error: unknown operand X; on a constant above 2047, print only NAME: error: constant K out of range.

Example

Input:

cCopy
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Output:

cCopy
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Requirements

1. Parse each line once into a list of operands and operators; each back end walks that list.
2. Byte counts come from the table above: the point is to see where x86's variable-length encoding wins or loses.

Hidden tests cover constant operands of both sizes, a constant first operand, multiplication by a constant, a function with no operator, and both errors.