Skip to main content

Loading page…

CPU Design: CPU & Computer Architecture | LowLevelCraft

Tracks
CPU & Computer Architecture
CPU Design

Subtrack

Sign in to track progress

CPU Design

Understand what happens inside your processor. Build a complete CPU from simple fetch-decode-execute to advanced pipelining with hazard detection.

~450 Minutes 10 Challenges

build a simple CPU simulator

About this subtrack

CPU Design implements fetch-decode-execute pieces, ALU paths, and early pipelines. For people searching "CPU simulator tutorial."

Tasks (10)

Implement Fetch-Decode-Execute Cycle for Toy ISA

Add ALU to CPU Emulator Supporting Arithmetic and Logic Ops

Add Register File: 8 General-Purpose Registers

Implement Memory-Mapped I/O: Map Address to Print Character

Add Branch Instructions: JMP, JEQ, JGT

Implement Simple Stack with PUSH and POP Instructions

Add CALL and RET Support for Subroutines

Implement 2-Stage Pipeline and Detect Hazards

Add 5-Stage Pipeline: IF, ID, EX, MEM, WB

Implement Forwarding to Eliminate Unnecessary Stalls