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Master the fundamental concepts of cpu design through this focused micro-challenge.
Three hints are available for this task, revealed one at a time inside the code workspace so you can struggle productively before seeing them.
Every task includes starter code, theory, and hidden tests so you can implement and verify locally in the browser.
How it worksEvery processor, from a 6502 emulator to a server Xeon, repeats fetch-decode-execute. The program counter (PC) points at the next instruction byte; the decoder maps opcode bits to control signals; execute updates registers, memory, or flags.
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| Opcode | Mnemonic | Effect |
|---|---|---|
| 0x01 | LOAD | R[d] = imm |
| 0x02 | ADD | R[d] += R[s] |
| 0x04 | HALT | stop |
A tiny program:
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For this exercise, you will implement this loop for the teaching ISA in the starter code. You will need correct PC advancement and operand decoding before adding the ALU, register file, and branches in later CPU design tasks.
Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.
For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.
Implement the fetch, decode, execute cycle of a tiny CPU. The program is a list of 16-bit machine-code words in memory. Each cycle fetches the word at PC, decodes its bit fields into an instruction, executes it, and prints what happened at each stage.
Four 8-bit registers R0: R3 (all start at 0; arithmetic wraps modulo 256) and a PC counting words from 0.
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| Opcode | Instruction | Effect |
|---|---|---|
| 0 | HALT | stop |
| 1 | LOAD Rd, imm | Rd = imm8 |
| 2 | ADD Rd, Rs | Rd = Rd + Rs |
| 3 | SUB Rd, Rs | Rd = Rd - Rs |
Fields an instruction doesn't use are ignored.
The program: hexadecimal words (with or without 0x), separated by spaces or newlines, loaded at address 0.
For each instruction:
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The machine stops on HALT, on an unknown opcode (DECODE illegal opcode 0xN then stop, no EXEC line), or when PC runs past the last word (print FETCH pc=N out of program). Then print:
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K counts instructions that executed, including HALT. Register values are decimal; ir is printed as 4 upper-case hex digits.
Input:
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Output:
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fetch, decode (into a struct with opcode/rd/rs/imm fields, using shifts and masks) and execute steps.PC advances during fetch.Hidden tests cover subtraction that wraps below 0, addition that wraps past 255, ignored fields, an illegal opcode, and a program without HALT.