Implement Memory-Mapped I/O: Map Address to Print Character

Topic Overview

I/O Without Special Instructions

Memory-mapped I/O maps device registers into the same address space as RAM. A store to address 0xFF00 might print a character instead of writing DRAM. Embedded ARM and AVR firmware uses this model exclusively.

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Decode-Time Address Check

The CPU does not need new opcodes. Existing LOAD/STORE instructions target either RAM or a device based on address decoding in the memory subsystem.

• RAM region: 0x0000 - 0x7FFF
• IO region: 0x8000 and above (example map)
• Side effects: IO writes may be irreversible (UART transmit)

For example, storing ASCII 72 ('H') to the print port should emit a character on the host console.

For this exercise, you will map one output address to printf or equivalent. This task asks you to extend mem_write with a device hook, the same pattern Linux uses when drivers map PCI BARs into virtual memory.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.

Your Task

Implement a CPU's memory-mapped I/O bus. The CPU only knows loads and stores. An address decoder decides whether each access goes to RAM or to a device register, such as a UART that transmits a character when you write to it or a status register that reports whether it's ready. Simulate the bus cycle by cycle, including the classic bug of writing to a busy UART.

Memory map

The UART is busy for the 2 cycles after it accepts a byte: a byte accepted in cycle t makes it busy during cycles t+1 and t+2. It is ready again from t+3.

Input

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Numbers are decimal or 0x hex. Cycles are numbered from 1.

Output

One line per access:

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(the write form uses the same bus-error messages). Addresses print as 4 upper-case hex digits, values as 2. At the end:

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Example

Input:

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Output:

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Requirements

1. One bus_read(addr) / bus_write(addr, value) pair that decodes the address and dispatches to RAM or a device handler.
2. The UART tracks the cycle until which it is busy; status reads compute readiness from the current cycle.

Hidden tests cover polling the status register until ready, reads of the write-only TX register and writes to the read-only status register, unmapped addresses, the LEDs, and non-printable bytes such as a newline.