Add 5-Stage Pipeline: IF, ID, EX, MEM, WB

Topic Overview

Classic Five Stages

Modern teaching pipelines use IF (fetch), ID (decode), EX (execute), MEM (memory), and WB (writeback). Each stage advances every cycle, so five instructions can be in flight at once when the pipe is full.

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Hazards Across Five Stages

Load-use hazards are the classic pain: a LOAD in EX produces data in MEM, but the next instruction needs it in EX one cycle later. You must stall one cycle or forward from MEM/WB.

For this exercise, you will refactor your CPU into five pipeline registers. You will need stage-accurate PC and register updates to match textbook timing diagrams before adding forwarding to remove unnecessary stalls.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.

Your Task

Build the classic 5-stage pipeline: IF (fetch), ID (decode + register read), EX (ALU, branch decision), MEM (load/store) and WB (register write). Up to five instructions are in flight at once. This version has no forwarding: an instruction must wait in ID until the registers it needs have been written back. Simulate it cycle by cycle, count stalls and flushes, and measure the speedup over a single-cycle CPU.

ISA

Registers R0: R7 (integers, start at 0) and 16 words of data memory (start at 0; the address is (Rs + off) mod 16). Labels are name: at the start of a line. Programs are well-formed.

Instructions are named I0, I1, … by position (labels and blank lines don't count).

Pipeline rules, per cycle

1. The register file writes in the first half of a cycle and reads in the second, so ID can read a value that WB writes in the same cycle.
2. Stall: if the instruction in ID reads a register that the instruction in EX or MEM will write, it stays in ID; IF also holds, and a bubble enters EX.
3. Branch: BNEZ is decided in EX. If taken, the instructions in ID and IF are flushed and IF fetches the target next cycle (this beats a stall).
4. Otherwise everything moves one stage forward and IF fetches the next instruction. Fetching stops after a HALT is fetched and restarts on a taken branch; past the end it yields nothing.
5. The run ends after the cycle in which HALT is in WB, or once the pipeline is empty. Give up after 300 cycles.

Output

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-- is an empty stage or bubble. Append stall Rn (the first conflicting source, in operand order: Rs, Rt for ADD/SUB, Rt, Rs for SW) or flush. Then:

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N counts instructions that reached WB, including HALT; CPI = C / N. A single-cycle CPU takes one cycle per instruction, but its clock period is five times longer than this pipeline's, so speedup = 5N / C. On the cycle limit, print cycle limit reached instead of the retired/CPI lines.

Example

Input:

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Output:

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Requirements

1. Five latch variables advanced together each cycle; hazard detection compares ID's sources with the destinations in EX and MEM.
2. Compute values functionally when an instruction is in EX (in program order), so the final registers match sequential execution.

Hidden tests cover a loop whose BNEZ is taken and then not taken, a store followed by a load from the same address, and a program without HALT.