Add ALU to CPU Emulator Supporting Arithmetic and Logic Ops

Topic Overview

Integrating the ALU

Your emulator already fetches and decodes instructions. Now the execute stage must dispatch arithmetic and logic opcodes to an ALU module that reads two register operands and writes back a result plus flags.

• Read: pull rs and rt from the register file
• Operate: ALU computes from opcode
• Write: store result into rd; update Z/N/C/V flags

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Operand Encoding

Teaching ISAs often pack register indices into the instruction byte. For example, bits 4-3 might select destination, bits 2-1 source A, bits 0 source B.

For this exercise, you will connect decode output to ALU operations for ADD, SUB, AND, OR, and NOT. This task asks you to close the loop from instruction bits to numeric results, the same execute-stage wiring QEMU's interpreter performs for each guest instruction.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.

Your Task

Give the toy CPU a real ALU and a flags register. Programs are now written in assembly text. Your emulator first assembles the whole program, then executes it. Every arithmetic or logic instruction goes through one alu(op, a, b) function that returns the result and updates the Z, C and N flags.

Machine

Four 8-bit registers R0: R3, all 0 at start. Flags Z, C, N, all 0 at start.

Z = result is 0; N = bit 7 of the result. Results are kept to 8 bits. Execution also stops after the last line.

Input

One instruction per line; mnemonics and register names are upper case, operands are separated by a comma and optional spaces. Blank lines are ignored.

Output

One line per executed instruction, echoing it in canonical form (OP Rd, Rs / OP Rd, imm with a decimal immediate / NOT Rd / HALT):

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Then a final line R0=a R1=b R2=c R3=d Z=z C=c N=n.

If any line fails to assemble, execute nothing and print only error line L: MESSAGE for the first bad line (L counts all lines from 1, including blank ones). The possible messages are unknown instruction WORD, bad operands and immediate out of range.

Example

Input:

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Output:

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Requirements

1. A two-pass structure: assemble every line into an instruction struct, then run.
2. All flag logic lives in the ALU function; the execute stage just calls it and writes back the result.

Hidden tests cover a borrow in SUB (C=0), an ADD that carries out to exactly 0, operands with no space after the comma, a blank line, instructions after HALT that must not run, and a program whose first bad line (counting a blank line) is an unknown instruction.