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Master the fundamental concepts of digital logic & boolean algebra through this focused micro-challenge.
You have read the whole brief, and the concepts above stay free on every task. Writing and running the code needs a plan.
Three hints are available for this task, revealed one at a time inside the code workspace so you can struggle productively before seeing them.
Every task includes starter code, theory, and hidden tests so you can implement and verify locally in the browser.
How it worksAn SR latch uses cross-coupled NOR (or NAND) gates to store one bit. Set (S) forces output high; Reset (R) forces it low. The forbidden S=1, R=1 state is why designers moved to safer clocked structures.
S=1, R=0: latch sets to 1S=0, R=1: latch resets to 0S=0, R=0: hold previous valueS=1, R=1: invalid (race condition)A D flip-flop samples input D only on a clock edge (rising or falling). Between edges the output holds stable, which is what register files and pipeline registers require.
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For example, if D=1 at the rising edge, Q becomes 1 and stays 1 until the next edge, even if D toggles wildly in between.
For this exercise, you will implement an SR latch and wrap it into a D flip-flop with enable. You will need edge-triggered behavior before building the 4-bit register that holds program state across clock cycles.
Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.
For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.
Simulate the two basic memory elements. First an SR latch built from two cross-coupled NOR gates, evaluated gate by gate until it settles, including the forbidden input that makes it oscillate. Then compare a level-sensitive D latch with an edge-triggered D flip-flop driven by the same clock and data.
State: Q, Qb, initially Q=0 Qb=1. The gates are
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Both gates update simultaneously from the current values. On sr S R, apply updates until an update changes nothing; the number of updates that changed something is the step count. If the latch is still changing after 10 updates, it oscillates: Q and Qb become unknown. An unknown latch is simulated from Q=0 Qb=0 on the next sr command.
Both start with Q=0, and the clock starts at 0. On clk C D (the new clock level and data):
C = 1, Q = D; otherwise it holds;D only on a rising edge (previous clock 0, new clock 1).cLoading…
The SR name is set (S=1, R=0), reset (S=0, R=1), hold (0, 0) or invalid (1, 1): printed whenever the latch settles. edge is rising, falling or none. Any other line, or arguments that aren't 0/1, prints error: bad command.
Input:
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Output:
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Hidden tests cover the invalid input S=R=1 followed by S=R=0 (oscillation) and recovery with set/reset, a clock held high while the data changes, and malformed lines.