CPU & Computer ArchitectureSIMD & VectorizationEasy

Benchmark Scalar Loop Performance

Master the fundamental concepts of simd & vectorization through this focused micro-challenge.

~30 minutes SIMD & Vectorization Ready to learn

Topic Overview

Baseline Scalar Performance

Before SIMD, establish how fast a plain C loop runs. Compiler unrolling, autovectorization, and profile-guided optimization can surprise you, so measure with optimization flags documented.

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Measurement Hygiene

Pin CPU frequency (cpufreq performance governor)
Warm caches or report cold vs warm separately
Repeat and take median; report variance

For example, multiplying two 1M-element float arrays might run at 200 MB/s scalar but jump an order of magnitude once vectorized.

For this exercise, you will benchmark element-wise multiply-add and record ns/element. This task asks you to save this scalar baseline because every SIMD task compares speedup against it.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

Trace first: walk one failing input by hand before changing random lines
Read the manual: skim the official doc for the mechanism named in this task
Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.

Implementation Task

Your Task

Establish the scalar baseline that every SIMD task in this track compares against. Implement the kernel y[i] = a · x[i] + y[i] (SAXPY on integers), verify it with a checksum, and model its cost across working-set sizes: small arrays stream from L1, larger ones from L2, the largest from memory. The model shows why a vectorised kernel can't beat a bandwidth limit.

Input

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Kernel

x and y are int32 arrays of length N, with x[i] = i mod 100 and y[i] = i mod 7. Compute y[i] = A · x[i] + y[i] for every i, in 32-bit wrap-around arithmetic, and checksum as the 64-bit sum of the resulting y[i].

Cost model

The working set is 8 · N bytes (both arrays). It is served by the first level whose capacity is at least the working set, else by memory. Cycles = N × that level's cycles per element.

Output

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The working set prints as N B below 1 KiB, X.X KiB below 1 MiB, else X.X MiB. Cycles have one decimal, elements/cycle two. At the end:

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listing every level in order, then memory, each with one decimal.

Example

Input:

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Output:

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Requirements

The kernel is one plain loop over int32_t arrays; the checksum proves the result is right before any SIMD version is compared with it.
The cost model is a separate function of the working-set size.

Hidden tests cover a working set exactly equal to a level's capacity (still fits), negative multipliers, a single-level hierarchy, sizes in MiB, and N = 1.