Build a 4-bit Ripple-Carry Adder

Topic Overview

Ripple-Carry Structure

A ripple-carry adder chains full-adders so each stage's Cout becomes the next stage's Cin. Bit 0 adds first; the carry ripples left until the MSB settles. This is slow in silicon (worst-case delay grows with width) but beautifully simple to simulate.

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Worked Example: 3 + 5

On four bits, 0011 + 0101:

• Bit 0: 1 + 1 + 0 gives sum 0, carry 1
• Bit 1: 1 + 0 + 1 gives sum 0, carry 1
• Bit 2: 0 + 1 + 1 gives sum 0, carry 1
• Bit 3: 0 + 0 + 1 gives sum 1, carry 0

Result: 1000 (decimal 8).

For this exercise, you will implement four chained full-adders and verify addition across random test vectors. This task asks you to expose carry timing: watch how a carry injected at bit 0 eventually reaches bit 3, the same propagation delay that motivates carry-lookahead in real CPUs.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.

Your Task

Chain four full adders into a 4-bit ripple-carry adder. The carry out of bit i is the carry in of bit i+1, so it "ripples" from bit 0 to bit 3. Trace the carry through every stage, and report both the unsigned carry-out and the signed overflow flag.

Input

One addition per line: A B CIN, where A and B are decimal integers in 0..15 and CIN is 0 or 1.

Output

For each line:

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• AAAA, BBBB, SSSS: 4-bit binary, most significant bit first.
• U: the 4-bit sum as unsigned (0..15). V: the same bits read as two's complement (−8..7).
• carry: carry out of bit 3: the unsigned result didn't fit in 4 bits.
• overflow: carry into bit 3 XOR carry out of bit 3: the signed result didn't fit.

Print a blank line between additions. If a line doesn't hold three integers with A, B in 0..15 and CIN in 0..1, print error: expected A B CIN with A,B in 0..15 and CIN in 0..1 instead (it still counts as one entry for the blank-line separation).

Example

Input:

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Output:

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Requirements

1. A full_adder(a, b, cin, &sum, &cout) function; the 4-bit adder calls it four times in a loop, feeding each carry-out forward. Don't use + on the operands.
2. Compute overflow from the two carries, not by re-doing the arithmetic.

Hidden tests cover unsigned carry without signed overflow, negative + negative overflow, 15 + 0 + 1, and out-of-range or malformed lines.