Understand the Reset Vector: Why CPU Starts at 0xFFFFFFF0

Topic Overview

Why the CPU starts at 0xFFFFFFF0

On x86, reset does not begin at address zero. The hardware fetches from 0xFFFFFFF0, sixteen bytes below the 4 GB line. In real mode only the low 20 bits matter, so the CPU effectively starts at 0xFFFF0 inside the BIOS ROM. For example, with CS=0xF000 and IP=0xFFF0, the physical address is 0xF0000 + 0xFFF0 = 0xFFFF0.

Reset vector mechanics

• Real mode on reset: 16-bit segmentation, 1 MB addressable without paging
• CS:IP at reset: CS=0xF000, IP=0xFFF0 on standard PC-class CPUs
• First bytes: Often a far jump to the main BIOS entry at another ROM address
• Compatibility: The 8086 placed reset near the top of the 1 MB map; modern CPUs preserve it

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• UEFI firmware still begins from this vector before switching modes
• QEMU models the same values, which is why monitor inspection matches datasheets
• Boot code you write later loads at 0x7C00, a different region entirely

Why for this exercise

You will explain the reset vector address and show the segment:offset math that yields 0xFFFF0. This exercise requires connecting the linear 0xFFFFFFF0 value to the 8086-era 1 MB real-mode view the first firmware instructions use.

Your Task

The 8086 forms a physical address as (segment << 4) + offset, but it has only 20 address lines, so a sum past 0xFFFFF wraps into the first megabyte. That is the behaviour the A20 gate later made switchable. Compute the address of each segment:offset pair, and count how many land on the real-mode reset vector, 0xFFFF0.

Input

N, then N lines SEGMENT OFFSET, both in hexadecimal.

Output

One line per pair, segment and offset as 4 uppercase hex digits and the address as 5:

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When the unmasked sum exceeded 0xFFFFF, the line ends with (wrapped at 1MB, 8086 has no A20). Finally, RESET-VECTOR 0xFFFF0 ALIASES: k, the number of pairs whose address is 0xFFFF0.