Master the fundamental concepts of build a mini kernel through this focused micro-challenge.
You have read the whole brief, and the concepts above stay free on every task. Writing and running the code needs a plan.
Three hints are available for this task, revealed one at a time inside the code workspace so you can struggle productively before seeing them.
Every task includes starter code, theory, and hidden tests so you can implement and verify locally in the browser.
How it worksThe Intel 8254 PIT channel 0 fires IRQ0 at a programmable rate via divisor latch. Kernels use it for time slices, jiffies, and sleep accounting.
Output frequency = 1193182 / divisor
1193 ≈ 1 kHz (1 ms ticks)For example, divisor 119318 yields roughly 10 Hz timer interrupts for coarse scheduling demos.
Programming the 8253/8254 PIT at 100Hz is literally how the Linux kernel's early boot timer worked before the APIC timer and HPET took over, and it remains the simplest way any teaching kernel like xv6 implements preemptive multitasking. Get the frequency divisor calculation wrong and your entire scheduler's sense of elapsed time drifts, silently breaking any timeout logic built on top of it.
Before you call the implementation done, walk failure modes on purpose. Test empty structures, single-element edge cases, maximum concurrency, and errno paths that must not crash the program. OS code usually fails in production when happy-path tests pass but invariants break under contention or memory pressure.
Keep structures small and name fields after kernel counterparts when possible. That lets you read man pages and kernel source side by side while you work. Print observable events during development; remove noisy logs once tests pass reliably.
You will program PIT registers and increment a tick counter in the IRQ0 handler. This exercise requires converting ticks to milliseconds in a kernel_sleep helper.
Program the 8253/8254 PIT, the timer that drives preemptive scheduling on a classic PC. Its input clock runs at 1193182 Hz. The kernel divides it by a 16-bit divisor to get the tick rate, then sends a command byte and the divisor's low and high bytes to the ports. Because the divisor is an integer, the real rate is never exactly what you asked for. Compute the divisor and the error, decode command bytes, and simulate how ticks drive a round-robin scheduler, including the drift that comes from the rounding.
| Command | Meaning |
|---|---|
freq HZ | program channel 0 for HZ ticks per second (mode 3, lobyte/hibyte) |
command CH ACCESS MODE | build a command byte (channel 0-2, access 0-3, mode 0-5, binary) and decode it |
decode HEX | decode an arbitrary command byte |
run MS ms quantum Q tasks N | simulate MS milliseconds at the current rate; switch task every Q ticks among N tasks |
round(1193182 / HZ), i.e. (1193182 + HZ/2) / HZ in integer arithmetic. A divisor above 65536 is too slow (minimum 19 Hz), and an HZ above 1193182 is too fast (maximum 1193182 Hz). A divisor of 65536 is written as 0x0000.1193182 / divisor, period = 10⁶ / actual µs, and error = (actual − HZ) / HZ × 10⁶ ppm.channel << 6 | access << 4 | mode << 1 | bcd. Access names: 0 latch count, 1 lobyte only, 2 hibyte only, 3 lobyte/hibyte. Modes: 0 interrupt on terminal count, 1 hardware one-shot, 2 rate generator, 3 square wave, 4 software strobe, 5 hardware strobe (6 and 7 alias 2 and 3).outb 0x43, 0x36, then outb 0x40, low byte, then outb 0x40, high byte.ticks = MS × 1193182 / (1000 × divisor) (integer). Each tick is charged to the current task. After every Q ticks the scheduler switches to the next task (task N−1 wraps to 0). Before any freq, the divisor is the power-on value 65536 (≈18.2 Hz).cLoading…
Note the drift: at "100 Hz" one second contains only 99 whole ticks.
Input:
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Output:
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& 0xFF and >> 8; print every port write through one outb helper.Hidden tests cover a 250 Hz kernel, the power-on rate, the minimum-frequency and too-fast errors, BCD and other modes decoded from raw bytes, a command with an invalid channel (command: invalid), and uneven task counts.