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Master the fundamental concepts of digital logic & boolean algebra through this focused micro-challenge.
You have read the whole brief, and the concepts above stay free on every task. Writing and running the code needs a plan.
Three hints are available for this task, revealed one at a time inside the code workspace so you can struggle productively before seeing them.
Every task includes starter code, theory, and hidden tests so you can implement and verify locally in the browser.
How it worksA 1-bit multiplexer (MUX) routes one of two data inputs to a single output, controlled by a select line S. When S=0, output follows I0; when S=1, output follows I1.
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MUX blocks appear everywhere: ALU operation select, register-file read ports, and memory bank switching in embedded SoCs.
A demultiplexer (DEMUX) is the inverse: one data input fans to one of two outputs based on S. For example, with D=1 and S=0, only O0 goes high while O1 stays 0.
For this exercise, you will build both circuits from AND, OR, and NOT gates. You will use the MUX in the 4-bit ALU task to choose between ADD and SUB results on the same datapath, which is exactly how real ALUs share hardware across operations.
Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.
For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.
Build multiplexers (many inputs → one output, chosen by select lines) and demultiplexers (one input → one of many outputs) from logic gates, then compose them: a 4-to-1 mux out of three 2-to-1 muxes, a 1-to-4 demux out of three 1-to-2 demuxes, and a shared wire that routes one of four sources to the matching destination.
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One command per line; all arguments are bits (0/1).
| Command | Output |
|---|---|
mux2 S D0 D1 | mux2 s=S -> out=X |
mux4 S1 S0 D0 D1 D2 D3 | mux4 s1=S1 s0=S0: lo=L hi=H -> out=X (d<N>) where N = 2·S1 + S0 |
demux2 S D | demux2 s=S d=D -> y0=. y1=. |
demux4 S1 S0 D | demux4 s1=S1 s0=S0 d=D: a=A b=B -> y0=. y1=. y2=. y3=. |
route S1 S0 D0 D1 D2 D3 | route sel=N: bus=X -> y0=. y1=. y2=. y3=.: bus = mux4(...), then demux4(S1, S0, bus) |
Errors: an argument that isn't 0 or 1 → error: inputs must be 0 or 1; wrong argument count → error: CMD takes K inputs; unknown command → error: unknown command WORD.
Input:
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Output:
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mux2 and demux2 are computed with the gate equations above (&, |, ! on single bits: no if/?: on the select line).mux4, demux4 and route are built only by calling the smaller circuits.Hidden tests exercise every select value of mux4/demux4, demux with d=0, route, and the three error messages.