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Implementation
Why This Matters
IPC, cache-miss rate, and branch-misprediction rate are the first three numbers Intel's own optimization manuals tell engineers to check, because they explain the gap between a CPU's theoretical throughput and what it actually delivers on Skylake- and Zen-class cores. Google's data-center teams read these same perf_event counters fleet-wide via 'perf stat' to decide whether a service is memory-bound before anyone touches a line of code.
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main.c
Workspace 1.0
Demonstrate understanding of CPU performance counters and their impact on performance.
Requirements:
Implement different code patterns (cache-friendly vs unfriendly)
Measure using perf stat with specific counters
Analyze cycles, instructions, IPC
Measure cache behavior (references, misses, miss rate)