Understand CPU Performance Counters: Cycles, Cache Misses, Branch Mispredictions

Topic Overview

Hardware Counters Tell You Why

Modern CPUs expose performance-monitoring units (PMUs) that count cycles, instructions retired, last-level cache misses, and branch mispredictions. Intel VTune, perf, and likwid all read the same counters. A loop can look innocent in source yet retire few instructions per cycle because cache misses dominate.

Core Events to Watch

Cycles measure wall time on CPU. cache-misses at LLC level often explain memory-bound loops. branch-misses spike when data-dependent branches defeat the predictor.

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• IPC below 1.0 on a tight loop often means stalls, not cheap math
• Counter multiplexing skews short runs; prefer runs longer than 1 second
• perf list shows events your CPU actually supports
• Correlate counters with source lines using perf annotate

Working Through the Exercise

Keep the relevant documentation open while you implement. When your output disagrees with the reference, trace one failing case by hand before changing random lines.

• Trace first: walk one failing input step by step
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

Why for this exercise

You will run perf stat on two versions of the same algorithm and compare cycles, cache misses, and branch misses. This exercise requires you to connect counter deltas to specific code changes, not just report raw numbers.

Your Task

Raw hardware counters from perf stat -e ... mean little on their own. Engineers turn them into ratios: IPC and CPI, cache and branch miss rates, misses per thousand instructions (MPKI), and, when the right events are available, Intel's top-down level-1 breakdown of pipeline slots. Build that analysis step: take recorded counter sets and produce the derived metrics and a verdict.

Input

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Counter keys: cycles instructions cache-references cache-misses branches branch-misses L1-dcache-loads L1-dcache-load-misses uops_issued uops_retired idq_uops_not_delivered recovery_cycles.

Rules

• Formulas:
  • IPC = instructions / cycles and CPI = cycles / instructions (2 decimals).
  • Miss rates are percentages (1 decimal), and MPKI = misses × 1000 / instructions (1 decimal).
  • All values are rounded half up. n/a is printed for a zero denominator.
• A section is printed only if its counters are present: cache (references + misses), L1D (loads + misses), and branches (branches + misses). A report needs cycles and instructions, otherwise it prints need cycles and instructions.
• Top-down (when all four uop/slot events are present):
  • slots = 4 × cycles;
  • frontend = idq_uops_not_delivered;
  • bad speculation = uops_issued − uops_retired + 4 × recovery_cycles;
  • retiring = uops_retired;
  • backend = the remaining slots (at least 0).
  • Each is shown as a percentage of the slots. The verdict is the largest category (the earliest one on ties).
• Heuristic verdict otherwise, the first rule that applies:
  • branch miss rate >= 5% → branch mispredictions are costly (>= 5% missed);
  • IPC < 1 and cache MPKI >= 10 → likely memory bound (IPC < 1, >= 10 cache MPKI);
  • IPC >= 2.5 → running efficiently (IPC >= 2.5);
  • otherwise no single obvious bottleneck.
  • The thresholds use truncated integer comparisons (IPC × 100, MPKI × 10, rate × 10).
• compare A B prints B's cycles and instructions as multiples of A's. If B took more cycles with at most 10% more instructions, it adds the stalls hint.
• Errors: run NAME: bad counter TEXT, report NAME: no such run, and compare: need two runs with cycles.

Output

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Example

Input:

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Output:

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Requirements

1. Normalise by instructions (MPKI), so runs that do different amounts of work can still be compared.
2. Use integer arithmetic for every ratio.

Hidden tests cover a branch-heavy run, a frontend-bound top-down profile, a run missing cache counters, L1D metrics, zero denominators, runs assembled over several lines, and malformed counters.