Build 4-bit Register Using D Flip-Flops

Topic Overview

Parallel Load Register

A 4-bit register is four D flip-flops sharing one clock and one write-enable. On each rising edge, when EN=1, all four D inputs copy into Q outputs simultaneously. When EN=0, the register holds its value.

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Registers are the fastest storage a CPU touches: reading R3 in your toy emulator should be a single-cycle operation, unlike RAM.

Why Width Matters

Four bits can hold values 0 through 15. That is enough for a nibble of BCD, a counter in an embedded timer, or the program counter in a minimal teaching CPU.

• Clock: synchronizes all four flops
• Enable: gates writes without stopping the clock
• Reset (optional): clears to zero on startup

For this exercise, you will stitch four D flip-flops into one loadable register and verify parallel writes. This task asks you to treat the register as the bridge between combinational logic (adders, MUXes) and sequential state machines in the hardware simulator ahead.

Working Through the Exercise

Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.

• Trace first: walk one failing input by hand before changing random lines
• Read the manual: skim the official doc for the mechanism named in this task
• Compare baselines: save measurements from the prior step so speedups are honest

For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.

Your Task

Build a 4-bit register from four D flip-flops. A write-enable signal decides whether the register loads new data on the next rising clock edge or keeps its value. Hardware can't "skip" a clock edge, so write-enable is implemented with a 2-to-1 mux in front of each flip-flop that feeds back the current value when WE = 0. An asynchronous clear resets the register immediately, without waiting for the clock.

Circuit

For each bit i (0..3):

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All bits start at 0, and the clock starts at 0.

Input

One signal update per line:

• CLK WE DDDD: the new clock level (0/1), write enable (0/1) and 4 data bits (most significant first).
• clr: asynchronous clear: Q = 0000 immediately. The clock level is unchanged.

Output

Number the lines from t=1 (errors are numbered too):

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mux is the value of the four mux outputs, computed from the register contents before this line. EVENT is load on a rising edge with WE=1, hold on a rising edge with WE=0, and - when there is no rising edge. A line is bad unless it is clr or three fields: a 0/1, a 0/1 and exactly four 0/1 characters.

Example

Input:

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Output:

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Requirements

1. Model the four flip-flops and four muxes explicitly (arrays of bits, or bit operations applied per bit), with edge detection on the previous clock level.
2. clr must not depend on the clock.

Hidden tests cover the clock held high while data changes (no new edge), clr in the middle of a sequence, and malformed lines.