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Master the fundamental concepts of digital logic & boolean algebra through this focused micro-challenge.
You have read the whole brief, and the concepts above stay free on every task. Writing and running the code needs a plan.
Three hints are available for this task, revealed one at a time inside the code workspace so you can struggle productively before seeing them.
Every task includes starter code, theory, and hidden tests so you can implement and verify locally in the browser.
How it worksA 4-bit ALU performs arithmetic and logic on two nibble-wide operands. A opcode line (often fed through a MUX) selects the operation: ADD, SUB, AND, OR, XOR, or NOT.
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The carry-out from bit 3 becomes the C flag your CPU will later branch on.
Real ALUs export status bits:
For example, 7 + 1 on four signed bits overflows because 0111 + 0001 wraps to 1000 (-8 in two's complement).
For this exercise, you will combine your adder, logic gates, and MUX into one selectable ALU. This task asks you to produce both the result nibble and flag bits, because the branching and pipeline tasks downstream read those flags to decide jumps.
Keep the relevant datasheet, ISA manual, or architecture textbook chapter open while you implement. When your output disagrees with the reference trace on the same program, the bug is usually a mis-decoded opcode, a stale register read, or a flag bit left unchanged after arithmetic.
For this exercise, you will use those habits while implementing the requirement in the starter code. Microarchitectural product names change across CPU generations, but the control ideas (fetch, bypass, cache lines, vector lanes) stay stable enough to debug from first principles.
Build a 4-bit ALU: a single circuit that computes ADD, SUB, AND, OR, XOR or NOT, chosen by a 3-bit opcode. Arithmetic goes through a ripple-carry adder. Subtraction reuses that same adder via two's complement, computed as A + NOT(B) + 1. Every result sets the four condition flags a CPU's branch instructions test.
| Op | Opcode | Result |
|---|---|---|
ADD A B | 000 | A + B (adder, carry-in 0) |
SUB A B | 001 | A + NOT(B) + 1 (adder with inverted B, carry-in 1) |
AND A B | 010 | bitwise AND |
OR A B | 011 | bitwise OR |
XOR A B | 100 | bitwise XOR |
NOT A | 101 | bitwise NOT of A |
Operands are decimal integers in 0..15. All results are 4 bits.
Z = 1 if the result is 0000.N = bit 3 of the result.C = the adder's carry out of bit 3 (ADD/SUB only; 0 for logic ops). For SUB, C=1 means no borrow (A ≥ B unsigned), the ARM convention.V = signed overflow = carry into bit 3 XOR carry out of bit 3 (ADD/SUB only; 0 for logic ops).One line per operation:
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BBBB is ---- for NOT. U and S are the result read as unsigned and as two's complement. Errors: error: unknown op WORD, error: NOT takes 1 operand / error: OP takes 2 operands and error: operands must be 0..15, checked in that order.
Input:
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Output:
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-.Hidden tests cover SUB of equal values (Z=1, C=1), signed overflow in SUB, ADD with unsigned carry, OR/XOR/NOT, and the three error messages.